
Titan tightly integrates mixed-signal implementation with digital implementation, circuit simulation, transistor-level extraction and verification – providing a quantum leap in ... ... analysis and verification platform. Unlike other design solutions, Titan tightly integrates mixed-signal implementation with digital implementation, circuit simulation, transistor-level extraction and verification – providing a quantum leap in efficiency and productivity for analog designers.
Because Titan is based on Magma's ...

Cost-effective access to NicheLite complements the architecture and peripherals of ST's STR91x family, which is optimized for high performance in ... ... 32-bit Flash microcontrollers featured for networking applications, lowering cost-of-entry to that of open-source offerings but with the advantage of vendor support facilities. Compared to other third-party stacks, NicheLite is also royalty-free, helping manufacturers predict and manage their production costs.
NicheLite, ...

The Stanford team configured Xtensa as 3-way issue VLIW processors with seven stage pipeline, 64 general purpose registers, a 32-bit ... ... a multiprocessor computing infrastructure for next generation applications. The Stanford Smart Memories Project has developed a prototype system-on-chip (SOC) design that provides the user the ability to program both the processor and the memory system of a chip-level multiprocessor. ...

NXP's FM-RDS chip sets a new standard in radio performance, with better channel separation, best-in-class sensitivity, very high selectivity and ... ... Philips, launched the world's smallest highly-integrated FM stereo radio IC with R(B)DS functionality, the TEA5990. NXP's FM-RDS chip sets a new standard in radio performance, with better channel separation, best-in-class sensitivity, very high selectivity and clear sound. The TEA5990 ...

The new 150 Gb/s core delivers the performance and bandwidth that new designs require, now with higher data transfer rates. ... ... 150Gb/s high speed Interlaken protocol IP core for use in ASIC designs. SLE's new Interlaken IP Core is now available with more than twice the performance of the standard 60Gb/s version. This new high-speed core delivers the performance and ...