Titan tightly integrates mixed-signal implementation with digital implementation, circuit simulation, transistor-level extraction and verification – providing a quantum leap in efficiency and productivity for analog designers. Titan is based on Magma’s unified data model, it works seamlessly with Magma’s Talus® digital IC implementation…

Magma® Design Automation Inc. (Nasdaq: LAVA), a provider of chip design software, announced Titan(tm), the first full-chip mixed-signal design, analysis and verification platform. Unlike other design solutions, Titan tightly integrates mixed-signal implementation with digital implementation, circuit simulation, transistor-level extraction and verification – providing a quantum leap in efficiency and productivity for analog designers.

Because Titan is based on Magma’s unified data model, it works seamlessly with Magma’s Talus® digital IC implementation, FineSim(tm) circuit simulation, QuickCap® TLx transistor-level extraction (also announced today) and Quartz DRC and Quartz LVS physical verification products. As a result, analog and digital design teams are no longer isolated and can have clear visibility into their counterparts’ design space.

Cost-effective access to NicheLite complements the architecture and peripherals of ST’s STR91x family, which is optimized for high performance in embedded networking applications. Cost-effective access to NicheLite complements the architecture and peripherals of ST’s STR91x family, which is optimized for high performance in embedded networking applications…

STMicroelectronics (NYSE: STM) has made the NicheLite(TM) TCP/IP stack available free of charge with its STR91x 32-bit Flash microcontrollers featured for networking applications, lowering cost-of-entry to that of open-source offerings but with the advantage of vendor support facilities. Compared to other third-party stacks, NicheLite is also royalty-free, helping manufacturers predict and manage their production costs.

NicheLite, from InterNiche Technologies, Inc., accelerates development of applications requiring Ethernet connectivity. ST and InterNiche, a specialist provider of embedded Internet Protocol software stacks, have tailored the standard stack for optimal performance with the STR91x. The stack capabilities can also be easily extended with add-on modules already available from InterNiche.

The Stanford team configured Xtensa as 3-way issue VLIW processors with seven stage pipeline, 64 general purpose registers, a 32-bit floating point using the TIE (Tensilica Instruction Extension) Language. Two Tensilica processors are placed in a tile, along with a number of programmable memory mats…

Tensilica, Inc. announced that Stanford University’s Smart Memories Project used Tensilica’s Xtensa LX2 configurable processor to develop a multiprocessor computing infrastructure for next generation applications. The Stanford Smart Memories Project has developed a prototype system-on-chip (SOC) design that provides the user the ability to program both the processor and the memory system of a chip-level multiprocessor. Using Tensilica allowed the Smart Memory team to focus on creating a flexible memory system that supports many different memory models, including message passing, coherent shared memory, and transactional memory. The design is currently being evaluated for possible commercial deployment by a couple of large semiconductor companies.