NicheStack release v3.1 provides a comprehensive update to InterNiche’s entire catalog of embedded networking stacks, device management applications, utilities and security protocols. NicheStack v3.1 product families offer comprehensive support of TCP/IPv4 and IPv6 networking and device management standards…
InterNiche Technologies has announced the release of its v3.1 product line and introduced implementations of RTP/RTCP for transport and control of real-time data and the SNTP time synchronization protocol as part of its core TCP/IP stack releases. As with all of its modules, RTP and SNTP have been designed specifically for use in embedded devices and to be portable to all microprocessor architectures and operating systems.
NicheStack release v3.1 provides a comprehensive update to InterNiche’s entire catalog of embedded networking stacks, device management applications, utilities and security protocols. In addition to new products, v3.1 delivers improved interoperability, higher efficiency and new features that respond to the growing demands of the device networking market.
The Questa Codelink product is an integrated, source-level debug environment targeting processor driven tests. Mentor developed Questa Codelink, a rich source-level debugger for RTL processor models supplied by ARM and MIPS…
Mentor Graphics Corporation (Nasdaq: MENT) announced immediate availability of the Questa® Codelink(tm) product, an addition to the Questa Functional Verification Platform designed to speed the validation of ASICs containing one or more embedded processors. The Questa Codelink product is an integrated, source-level debug environment targeting processor driven tests.
Use of sign-off accurate, RTL processor models to drive cycles into multi-core SoC designs is a common practice among hardware verification engineers. This method of test is identical to the SoC’s actual operation and provides highly effective functional verification. A major limitation to this approach is the lack of an effective debug environment. Isolating the cause of a failing processor driven test is a tedious and time consuming process as RTL processor models delivered by the core vendor provide little or no debug visibility.
STMicroelectronics’ adoption of Tachyon OPC+ combined with their current use of Tachyon Lithography Manufacturing Check (LMC), a model-based, full-chip, through-process-window lithography verification solution. Brion is committed to delivering STMicroelectronics a comprehensive lithography solution to enable current and future development of semiconductor devices…
Brion Technologies announced that STMicroelectronics is producing 55 nanometer (nm) and 45nm devices using Brion’s Tachyon(tm) OPC+ optical proximity correction (OPC) solution. This follows the successful completion of the companies’ earlier OPC joint development program. STMicroelectronics’ adoption of Tachyon OPC+ combined with their current use of Tachyon Lithography Manufacturing Check (LMC), a model-based, full-chip, through-process-window lithography verification solution, for production at 90nm, 65nm and 45nm nodes provides STMicroelectronics an integrated computational solution.
“Tachyon’s predictable run times, reliable performance and yield-sensitive inspection has had a positive impact on our advanced OPC flow deployment process,” said Joël Hartmann, Silicon Technology Development director for STMicroelectronics, in Crolles, France. “Brion provides a clear economic benefit by delivering optimal cost of ownership as well as competitive technical solutions. We look forward to continuing this extremely productive collaboration.”