The RTL to GDSII Reference Flows are available for three configurations of the ARM Cortex-A9 processor: single core, dual Cortex-A9 MPCore(tm) multicore processor and quad Cortex-A9 MPCore(tm) multicore processor. The reference methodologies represent what engineers can expect while doing actual tapeouts, including the necessary steps for silicon-ready design, such as timing analysis for on-chip variation (OCV), clock uncertainty and signal integrity (SI)...
Continue reading »
The PROC_SoC family is designed to debug and verify SoC designs of diverse design styles. The New Generation PROC_SoC has doubled the capacity of the system by incorporating Altera's new Stratix; III EP3SL340, the world's largest and fastest FPGA. The PROC_SoC has a unique, flexible interconnect topology that allows any FPGA device to directly connect with large numbers of pins to any other programmable device in the entire system...
Continue reading »
The Noise Analysis Tool is insidious to GHz nanometer-scale analog and RF CMOS circuit performance. The Noise Analysis Tool include Analog FastSPICE(tm) circuit simulation, Noise Analysis Option(tm) device noise analyzer, RF FastSPICE(tm) periodic analyzer, and PLL Noise Analyzer(tm) stochastic nonlinear engine...
Continue reading »
The Latest Releases UltraSuite extend the Stonestreet One Wireless USB capabilities of its UltraSuite software to UWB silicon platforms which support the USB Implementers Forum (USB-IF) WHCI specification, including the new Alereon AL5350 / AL5100 chipset. This new UltraSuite and WiCenter WHCI capability expands robust software solutions for UWB silicon partners and OEM customers alike...
Continue reading »
