The Active-HDL 8.1 introduces a first-to-market FPGA simulator supporting assertions and functional coverage in SVA, PSL and OVA at an affordable price. Active-HDL is a mixed-language HDL simulator that offers project management, graphical design creation and support for all leading FPGA vendors from a single integrated design environment. Active-HDL 8.1 includes enhanced support for VHDL 2008 (IEEE Standard P1076-2008) including new constructs and libraries. Active-HDL 8.1 supports new and updated libraries including: Assertions, OVL 2.2 and VTL…
Aldec Brings Assertions to FPGA Designers with the Release of Active-HDL 8.1
Aldec, Inc., a pioneer in mixed-language simulation for ASIC and FPGA devices, announced the release of Active-HDL 8.1. The new release introduces a first-to-market FPGA simulator supporting assertions and functional coverage in SVA, PSL and OVA at an affordable price. Other improvements in this release include Verilog® simulation performance speed-up and support for additional VHDL 2008 language constructs. Active-HDL is a mixed-language HDL simulator that offers project management, graphical design creation and support for all leading FPGA vendors from a single integrated design environment.
SPAUI and RXAUI are optimized for Altera’s Stratix II GX, Stratix IV, and Xilinx Virtex 5 LXT / FXT devices to provide a compelling solution for storage, telecommunications, and data center applications. MorethanIP’s offering of SPAUI and RXAUI IP cores include a configurable SPAUI MAC, a programmable four-Lane PCS (Physical Coding Sub-layer) and a programmable two-Lane XAUI PCS (also known as RXAUI)…
MorethanIP Releases the Industry First Complete SPAUI and RXAUI Solution for FPGA and ASIC
Dune Networks, a leading provider of networking devices for Metro Ethernet, Enterprise and Data Center platforms and MorethanIP announced the immediate availability of the industry’s first SPAUI and RXAUI intellectual property (IP) cores for FPGAs and ASICs. MorethanIP’s SPAUI and RXAUI are optimized for Altera’s Stratix II GX, Stratix IV, and Xilinx Virtex 5 LXT / FXT devices to provide a compelling solution for storage, telecommunications, and data center applications. The identical cores can also be targeted seamlessly to ASIC and Structured ASIC, providing a low-risk path to cheaper devices.
The P220 and P230 devices in the Petra family, providing 40Gbps and 80Gbps full-duplex traffic management and fabric access functionality, respectively. The P220 and P230, together with the new generation of classification devices, enable the economic design of non-blocking switches with deep buffering and densities of hundreds of 10GE ports in a single shelf. The PETRA P220 and P230 support multiple interfaces on the line side enabling the connection of a wide range of Network Processors, Packet Processor devices, and FPGA devices. The P220 and P230 provide DRAM-based, deep packet buffering, which enables comprehensive traffic management, and integrate with a fabric interface that facilitates a Clos mesh fabric interconnect…
Dune Leads the Revolution of 10GE Ethernet Switches with the Introduction of the PETRA Family
10Gbps to 10Tbps non-blocking Ethernet switching shelves with 100ms buffers for Carrier Ethernet, Enterprise and Data Center networks