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Embedded Systems and Microcontroller Electronics Daily News for Developers and Decision Makers
The increasing demand for high-performance digital signal processing has led designers to a combined DSP processor and FPGA co-processor architecture. The new Co-Processing SpeedWay helps students leverage the benefits of high-level processor-based software design with the parallel DSP computation power of FPGAs. By taking the new Co-Processing SpeedWay Workshop, developers will learn a design methodology that lets them use FPGA co-processing to improve overall system performance without requiring knowledge of RTL design flows..
The DFI specification 2.1 extends support to the latest LPDDR2 memory technology and enables new features including frequency change support and low-power PHY options. The collaborative technical working group includes representatives from ARM, Denali, Intel, LSI, Samsung, and STMicroelectronics. This technical group is enhancing the specification with several low-power features aimed at speeding LPDDR memory system design and integration, and reducing verification costs. The DFI specification 2.1 enables a new low-power PHY interface that enables the controller to provide information to the PHY about the state of the system...

Parani-SD1000 is the latest release of the popular Parani-SD series Bluetooth-Serial adapter products from SENA, which have been widely used to build wireless M2M (Machine-to-Machine) communication environment. Parani-SD1000 is an ideal solution to replace wired serial cabling system by using wireless Bluetooth technology. It supports latest Bluetooth Specification 2.0+EDR (Enhanced Data Rate) which is more powerful and stable compared to previous Bluetooth standards..
The Quartus II software version 8.1 is the latest release of Quartus II software continues the company's history of delivering high-density FPGA compile times three times faster than other FPGA-vendor supplied development software, based on internal benchmarks. This latest Quartus II software enable design teams to close timing and power faster, lower R&D costs and shorten time to market..
