The CAT5270 and CAT5271 are two new Digitally Programmable Potentiometer (DPP) ICs suitable for high accuracy and stability for variable resistance adjustment applications in a wide range of industrial and consumer products. The CAT5270 and CAT5271 are dual-channel digital potentiometers with 256 resistor taps for fine resolution adjustment and an I2C-compatible interface for maximum interoperability. The new ON Semiconductor DPPs feature a volatile wiper register making them ideal for applications using a microcontroller (MCU) with on-chip memory for wiper recall, or for systems that do not require memory. They also provide a low-noise, reliable and space-saving alternative to mechanical potentiometers with the added benefit of immunity to dust / dirt contamination and vibration. The CAT5270 allows microprocessor control of up to 16 devices from a single bus, while the CAT5271 offers a single, fixed address. The CAT5270 and CAT5271 are insensitive to mechanical vibrations, shock, oxidation, dust, dirt and other contamination and are a fraction of the size of mechanical potentiometers. The CAT5270 and CAT5271 digitally programmable potentiometers are supplied in 14-lead TSSOP and 10-lead MSOP packages, respectively...
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ST’s LIS331HH motion sensor is three-axis sensor with digital output that can detect accelerations up to 24g, or about 5x the force created by a Formula One car under heavy braking. The LIS331HH’s market-unique combination of multiple full-scale ranges above 10g with small size, high resolution, low power consumption and smart embedded features enables high-precision motion sensing in a wide range of consumer and industrial applications. ST’s LIS331HH MEMS accelerometer provides extremely accurate output across full-scale ranges of ±6/±12/±24g. The medium-g sensing enables high-level vibration monitoring and high-shock detection without any loss of information. In game applications, medium-g detection enhances user interfaces, adding previously unseen levels of realism. ST’s LIS331HH motion sensor can be programmed to work in the sleep-to-wake-up mode. In this mode, the accelerometer keeps the read chain active, consuming less than 10uA, and wakes up when an event occurs, automatically increasing the output data rate. The LIS331HH is pin-to-pin- and firmware-compatible with all low-g sensors in the LIS331DL/DLx families. Housed in an environment-friendly 3 x 3 x 1 mm3 package...
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The ADS8556, ADS8557 and ADS8558 offer a sampling range of 730 kSPS and signal-to-noise ratio (SNR) up to 91.5 dB, and include the industry's only simultaneous sampling ADC that offers true, 16-bit no missing codes (NMC) performance. The new ADCs allow designers to maximize performance when connecting to a wide range of inputs or sensor types in applications including multi-axis motor control, simultaneous data acquisition, robotics, power quality management and power protection. The ADS8556 is available today in an LQFP-64 package and is pin-compatible with the 14-bit ADS8557 and the 12-bit ADS8558...
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The New Cypress’s 65-nm 144-Mbit QDRII, QDRII , DDRII and DDRII memories leverage 65-nm process technology developed with foundry partner UMC. They feature the market’s fastest available clock speed of 550 MHz and a total data rate of 80 Gbps in a 36-bit I/O width QDRII device, and consume half the power of 90-nm SRAMs. They are ideal for networking applications, including Internet core and edge routers, fixed and modular Ethernet switches, 3G base stations and secure routers, and also enhance the performance of medical imaging and military signal processing systems. The devices are pin compatible with 90-nm SRAMs, enabling networking customers to increase performance and double address table or packet buffer size while maintaining the same board layout. The New 65-nm QDR and DDR SRAMs offer up to 50% lower standby and dynamic current consumption, enabling the new wave of “green” networking infrastructure applications. The QDRII and DDRII devices have On-Die Termination (ODT), which improves signal integrity, reduces system cost, and saves board space by eliminating external termination resistors. The 65-nm devices use a Phase Locked Loop (PLL) instead of a Delay Locked Loop (DLL), which enables a 35 percent wider data valid window to simplify board-level timing closure and enhance compatibility with third-party processors...
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