Arasan Chip Systems Releases MIPI(R) High Speed Synchronous Interface (HSI) Controller IP and Software Stack

High Speed Syncronous Interface (HSI) is a fullduplex, low latency protocol, that is optimized for die-level interconnect between an Application Processor and a Baseband chipset. The HSI Controller IP and Software Stack are compliant with the HSI v1.0 specification. The IP core is compliant with the HSI Physical Layer Draft v1.1. By integrating this standard interface, application processors and wireless chipset developers are assured of an ecosystem of inter-operable components which can be combined to develop region and application specific mobile platforms. The layered HSI Software Stack is architected to be easily portable to multiple OS’s and hardware platforms. The stack can also be used on SoC’s that have multiple HSI interfaces. The stack supports multiple priority levels per logical channel and DMA modes for efficient data transfer…

MIPI HSI IP Block Diagram

MIPI HSI Compliant

• HSI V1.0 Specification
• HSI Physical Layer Draft Version 1.1.00

Full-Duplex High Speed Serial Interface

• Up to Eight (8) logical transmit and receive channels

Configurable Channels

• Bandwidth – Throughput weighted per channel
• FIFO Size
• Transmission Bit Rate
• Transmission Modes
• Receiver Data Flow
• Slave DMA or PIO

Bit Transmission Modes (Tx and Rx)

• Stream Transmission Mode
• Frame Transmission Mode

Receiver Data Flow

• Synchronized Data Flow
• Pipelined Data Flow
• Receiver Real-time Data Flow

Maximum bandwidth:

• 200 Mbps in each direction (Full-duplex)

Transmit arbitration support

• Round-robin
• Priority-based

Mode support

• PIO mode
• SDMA mode

Data time out for receive operation

Clocking

• Clock Gearing – Mechanism to reduce power by
clock control
• Dynamic clock frequency change – Optimizing bus
power consumption
• Clock recovery mechanism – Receiver

Supports all HSI Commands
Interface Support

• AHB, APB, AXI, OCP & other custom buses

HSI Stack Architecture
(Pictures: Arasan)

Features:

Compliance

• MIPITM HSI v 1.0

Development Environment

• x86 platform
• Linux OS GNU
• OS and HW independent architecture
wrapped around OS and HW abstraction
layer
• Configurable bus master and slave DMA
model support
• Portable to other environments

Protocol Features

• Data link protocol layer – general and
audio data
• Break event handling and option to send
Break command at API layer
• Runtime configurability for hardware
parameters
• Error detection and recovery

API Interface

• Generic API interface for device operations
• Break event transmission for synchronization

Quality of Service

• 8 priority levels for logical channel
• Special latency handling requirements for
a connection

Software Key features

• Aging of packets handling
• Event notifications
• Parallel communications on multiple links

Testing Aid

• Test stub to validate while in development