ARM Develops Two Cortex-A9 MPCore Hard Macro Implementations for the TSMC 40nm-G Process

Feature-rich consumer and enterprise devices require very high levels of processor performance in the tight power envelopes necessary for compact, high-density and thermally constrained environments. To meet these requirements ARM has combined high-performance processor and fabric IP with optimized ARM physical IP to develop two multi GHz-level Cortex-A9 MPCore hard macro implementations to provide very high performance within a leadership power profile. The two Cortex-A9 MPCore hard macro implementations for the TSMC 40nm-G process, enable silicon manufacturers to have a rapid and low risk route to silicon for high-performance, low-power Cortex-A9 processor-based devices. The speed-optimized hard macro implementation will enable devices to operate at frequencies greater than 2GHz. The dual core hard macros are the result of significant development investment in physical IP by ARM combined with its broad processor and fabric IP portfolio and leading-edge implementation flows from the EDA industry. Advanced physical IP techniques have enabled critical circuits within the design to be replaced with highly tuned logic cells and memories, increasing performance while lowering overall power consumption…

Cortex A9 MPCore Block Diagram (Click for Enlarge)
(Picture: ARM)