HDL Design House Unveils the VITAL HVT 25VF Behavioral Simulation Model
HDL Design House announced the VITAL HVT 25VF behavioral simulation model that fully compatible with Silicon Storage Technology SST 25VF064C, 64 Mbit SPI Serial Dual I / O Flash, described in the S71392-03-000 9.12 specification. The HVT 25VF are available through SPI (Serial Peripheral Interface) bus compatible protocol. SPI-bus control system consists of four control lines, chip enable (CE #) is used to select the device, and data can be obtained via a serial data input (SI), Serial Data Output (SO) and Serial Clock (SCK). The HVT 25VF supports both Mode 0 (0,0) and Mode 3 (1,1) operations SPI bus. Memory organization the HVT 25VF Super Flash memory array erased in a single 4 KByte erasable sectors with 32 KByte overlay blocks and 64 KByte overlay erasable blocks.
The VITAL HVT 25VF behavior model completely simulates the functionality of the actual behavior of the component to all components of the behavior of the time. This means full functionality, timing of inputs and outputs, all the necessary connections between the input signals (Setup / Hold, pulse with, etc.) and all the delays between the inputs and outputs. In the event of time constraints are broken, the VITAL HVT 25VF behavior model defines the possible violation and reports on the standard functions of vital importance. The code is written in Verilog and the model is very portable set of simulators.
The VITAL HVT 25VF behavioral model can be used for board-level and/or system level verification. In test environment, the device under test (DUT) is connected to the VITAL HVT 25VF component.
The VITAL HVT 25VF behavior models can be used along with HDL DH SPI Flash Memory Controller IP Core (HIP 3100). The HIP 3100 IP Core is advanced controller for SPI flash memory which the host CPU burden from direct data transfer control of PPI flash memory. The host CPU can program SPI controller specifying the type of data transfer (SPI instruction, address, data, etc.) and SPI controller executes requested transfer.
VITAL HVT 25VF High Level Block Diagram
(Picture from HDL Design House Website)
More information about Behavioral Model can be found at HDL Design House Website