Intel Introduces 22nm 3-D Tri-Gate Tansistors

Intel Corporation Announced a significant breakthrough in the evolution of the transistor, the microscopic building block of modern electronics. For the first time since the invention of silicon transistors over 50 years ago, transistors using a three-dimensional structure will be put into high-volume manufacturing. Intel will introduce a revolutionary 3-D transistor design called Tri-Gate, first disclosed by Intel in 2002, into high-volume manufacturing at the 22-nanometer (nm) node in an Intel chip codenamed “Ivy Bridge.” A nanometer is one-billionth of a meter.

The three-dimensional Tri-Gate transistors represent a fundamental departure from the two-dimensional planar transistor structure that has powered not only all computers, mobile phones and consumer electronics to-date, but also the electronic controls within cars, spacecraft, household appliances, medical devices and virtually thousands of other everyday devices for decades.

Intel’s 3-D Tri-Gate transistors enable chips to operate at lower voltage with lower leakage, providing an unprecedented combination of improved performance and energy efficiency compared to previous state-of-the-art transistors. The capabilities give chip designers the flexibility to choose transistors targeted for low power or high performance, depending on the application.

The 22nm 3-D Tri-Gate transistors provide up to 37 percent performance increase at low voltage versus Intel’s 32nm planar transistors. This incredible gain means that they are ideal for use in small handheld devices, which operate using less energy to “switch” back and forth. Alternatively, the new transistors consume less than half the power when at the same performance as 2-D planar transistors on 32nm chips.

The 3-D Tri-Gate transistors are a reinvention of the transistor. The traditional “flat” two-dimensional planar gate is replaced with an incredibly thin three-dimensional silicon fin that rises up vertically from the silicon substrate. Control of current is accomplished by implementing a gate on each of the three sides of the fin – two on each side and one across the top — rather than just one on top, as is the case with the 2-D planar transistor. The additional control enables as much transistor current flowing as possible when the transistor is in the “on” state (for performance), and as close to zero as possible when it is in the “off” state (to minimize power), and enables the transistor to switch very quickly between the two states (again, for performance).

Intel’s 3-D Tri-Gate transistor structure provides a way to manage density. Since these fins are vertical in nature, transistors can be packed closer together, a critical component to the technological and economic benefits of Moore’s Law. For future generations, designers also have the ability to continue growing the height of the fins to get even more performance and energy-efficiency gains.

The 3-D Tri-Gate transistor will be implemented in the company’s upcoming manufacturing process, called the 22nm node, in reference to the size of individual transistor features. More than 6 million 22nm Tri-Gate transistors could fit in the period at the end of this sentence.

22nm 3-D Tri-Gate Tansistors
(Photo from Intel Website)

More information about 3-D Tri-Gate Tansistors can be found at Intel Website