Lattice Semiconductor Announces Serial RapidIO 2.1 Endpoint Soft IP Core for the LatticeECP3 FPGA family
The RapidIO Interconnect Architecture is an industry-standard, packet-based interconnect technology that provides a reliable, high-performance interconnect between NPUs (network processing units), CPUs (central processing units), and DSPs (digital signal processors). Serial RapidIO enables chip-to-chip, board-to-board, and system-to-system communications and is targeted at the networking, embedded, and storage markets. RapidIO has won broad acceptance in wireless infrastructure applications, where it is used as a primary interconnect for DSP clusters in baseband processing. In the past, vendors had to rely on expensive, premium FPGAs for these applications. However, the combination of the Serial RapidIO 2.1 IP core and Lattice’s low-cost mid-range FPGA like the LatticeECP3 or LatticeECP2M now allows customers to develop low-power infrastructure solutions for 3G, LTE and WiMAX without sacrificing performance or cost…
Serial RapidIO 1x Physical Layer Block Diagram
(Picture: Latticesemi)
|
