Synopsys Announces Full Range of Silicon-Proven DDR3 and DDR2 IP Solutions for SoC Designs

By pur, Thursday, August 14th, 2008
Category: IC, Chip, SoC, IP Core

The DesignWare DDR IP solutions deliver memory system performance of up to 1600 Mbps, the maximum data-rate of the JEDEC DDR3 specification. The solutions include configurable protocol and memory controllers, integrated mixed-signal PHYs including I/Os and verification IP. The DesignWare DDR IP portfolio provides designers with scalable solutions that help reduce risk and speed time-to-market for applications such as digital home, digital office, data center and storage. The comprehensive DesignWare DDR IP portfolio consists of three product lines including DDR3/2, DDR2/3-Lite and DDR2/DDR, all of which have been validated and fully characterized in Synopsys’ silicon test chips and support two generations of DDR SDRAM. Each of the three DesignWare DDR IP product lines consists of a complete solution including configurable memory and protocol controllers, integrated PHY and verification IP…

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