Synopsys Announces Immediate Availability of DesignWare MIPI M-PHY IP for Next-Generation High-Speed Interfaces
Synopsys announced immediate availability of the DesignWare® MIPI M-PHY® IP for next-generation high-speed interfaces based on the newly ratified MIPI® Alliance M-PHY specification. With this latest addition to the DesignWare MIPI IP portfolio, Synopsys is the first provider to offer a comprehensive solution of a controller and PHY IP for both the MIPI DigRF(SM) v3 (2.5G/3.0G) and v4 (4G) standards. Incorporating both standards in a mobile device brings the benefit of the faster 4G standards while preserving broad coverage by using 2.5G/3.0G as a fallback mode. The configurable MIPI DigRF V4 Master Controller and M-PHY hard macro are compliant to the MIPI Alliance specifications. Utilizing a single-vendor solution enables designers to lower the risk and cost of integrating these MIPI interfaces into baseband and application processor integrated circuits (ICs), speeding time-to-market of advanced semiconductor solutions for LTE and Mobile WiMAX.
The DesignWare MIPI M-PHY implements all required physical layer functionality defined in the MIPI DigRF v4 specification. The DesignWare MIPI M-PHY is designed to meet the stringent power consumption guidelines of the MIPI M-PHY specification, keeping the energy expenditure below 15pJ/bit for typical LTE applications. The integrated analog Phase Lock Loop (PLL) and biasing block are designed to help guarantee the integrity of the high-speed clocks and signals required to meet the strict timing requirements of the protocol, affording designers a robust and low risk solution. In addition, the DesignWare MIPI M-PHY supports the optional dithering functionality defined in the MIPI DigRF v4 specification to further lower Electromagnetic Interference (EMI).
DesignWare MIPI IP portfolio
(Photo from Synopsis Website)
More information about DesignWare MIPI M-PHY IP can be found at Synopsys Website