MuChip has deployed the Virtuoso-based RF design flow, which provides wireless chip designers access to improved design performance and a more predictable design cycle. For a recent bluetooth 2.1 RF IC and 2.4GHz ISM band high data rate RF transceiver tapeout, MuChip relied on the complete Cadence design flow, including Cadence Virtuoso® front-to-back products, to quickly and accurately verify, simulate and analyze its RF custom ICs. MuChip used the Virtuoso UltraSim product for full-chip simulation, which provided a six to seven times performance gain over previous project results. MuChip used the XL version of the Cadence Spectre® Circuit Simulator to improve numerical analysis, harmonic simulation and speed device model evaluation…
MuChip Adopts Cadence Virtuoso Solution to Speed Wireless RF SoC Design Development
Cadence Holistic RF Solutions Deployed for Advanced RF Designs Targeting Wireless Communication Applications
The enhancement of ARM Development Suite will allow developers using this chip to get programs up and running even more quickly and thereby speed up the whole development process. The Atmel AT91SAM9263 chip, based upon the ARM926EJ-S processor core, features a wide range of on-chip peripherals including an LCD controller and a 2D graphics accelerator. It also features a 9-layer bus matrix which, in conjunction with dual external bus interfaces and suitably arranged memories, enables direct memory access (DMA) from the LCD controller to the graphics memory to take place without disturbing program execution…
CROSSWARE ENHANCES ARM SUITE WITH GRAPHICS SUPPORT FOR ATMEL AT91SAM9263
- GUI Code Creation Wizards for LCD Controller and Graphics Accelerator
- Example programs using LCD Controller and Graphics Accelerator
- Support for Vector Fonts using FreeType
ispLEVER Classic v1.2 Design Tool Suite supports all Lattice SPLD, CPLD and select FPGA families. ispLEVER Classic v1.2 Design Tool Suite now provide full production support for the recently released ultra low power ispMACH® 4000ZE CPLD family and also include user-friendly support for several innovative new silicon functions. ispLEVER Classic 1.2 also includes the newest versions of Synopsys’ Synplify synthesis and Aldec’s Active-HDL simulator EDA tools. The release of the ispLEVER Classic tool suite offers users immediate access to Lattice’s exciting new PLD technology…
LATTICE ispLEVER CLASSIC DESIGN TOOLS NOW SUPPORT NEW CPLD FAMILY
Full Production Support for Ultra Low Power ispMACH 4000ZE CPLDs
Lattice Semiconductor Corporation (NASDAQ: LSCC) announced the immediate availability of its ispLEVER® Classic version 1.2 design tool suite. The tool suite supports all Lattice SPLD, CPLD and select FPGA families. Lattice’s ispLEVER Classic tools now provide full production support for the recently released ultra low power ispMACH® 4000ZE CPLD family and also include user-friendly support for several innovative new silicon functions. ispLEVER Classic 1.2 also includes the newest versions of Synopsys’ Synplify synthesis and Aldec’s Active-HDL simulator EDA tools.