The inrevium TB-5V-LX330T/SX240T/FX200T-PCIE-EX is equipped with the highest density Virtex-5 FPGAs with high speed serial I/O and PCI Express Gen 1 and Gen 2 interfaces. Expansion I/O connectors enable a wide variety of interfaces by connecting various optional boards such as DVI, AD/DA, FCRAM. The inrevium TB-5V-LX330T/SX240T/FX200T-PCIE-EX includes reference designs to reduce development period of FPGA designs and software designs…

TOKYO ELECTRON DEVICE ANNOUNCES SIMULTANEOUS RELEASE OF THREE HIGH-DENSITY FPGA PCI EXPRESS PLATFORMS

Significantly reduce development period of FPGA based High-Speed applications

Tokyo Electron Device Limited (TED) has announced the release of three inrevium Virtex®-5 High-Density PCI Express Platforms. These PCI Express Gen 1 & 2 capable platforms utilize Xilinx Virtex-5 LX330T, SX240T and FX200T FPGAs, the highest density FPGAs available. “In recent years, high performance embedded systems require FPGAs with higher speed, density and performance,” said Yasuo Hatsumi, Director and Xilinx Product Manager, PLD Solution Division of TED. “Further, with shorter product life cycles, customers demand FPGA evaluation platforms that are flexible and meet diversified needs.”

The expanded Cadence portfolio focuses on standard protocols for the wireless, networking, storage and multimedia vertical markets, enabling system verification and validation engineers to ramp-up their environment in days, improving the final quality of their software and hardware for a low-risk path to first-working silicon with first-working software. The portfolio also reinforces the Cadence VIP leadership position in Open Verification Methodology (OVM) advanced testbench VIP…

Cadence Expands Portfolio of System-Level Verification IP and SpeedBridge Adapters to Boost Acceleration and Emulation Performance

The New System VIP and SpeedBridge Adapters Speed Up Time to Market and Improve Quality, Further Extending Cadence Leadership in VIP Portfolio Breadth and Depth

Jivaro-for-GoldenGate is a parasitic model order-reduction tool designed for use with the company’s GoldenGate RF simulator software. Jivaro-for-GoldenGate is expected to enhance RFIC simulation speed and capacity with negligible loss in accuracy. Jivaro-for-GoldenGate is designed in cooperation with edXact, a company that provides high-precision, high-performance technology for backend physical verification. Jivaro-for-GoldenGate fills the gap between circuit extraction and circuit simulation created by an increased number of parasitic components (resistance, capacitance, self and mutual inductance) required to model the physical reality of circuit interconnects, substrates or packages…

Agilent Technologies’ Parasitic Reduction Tool Enhances RFIC Simulation Speed, Capacity While Preserving Accuracy

Agilent Technologies Inc. (NYSE:A) announced Jivaro-for-GoldenGate, a parasitic model order-reduction tool designed for use with the company’s GoldenGate RF simulator software. Jivaro-for-GoldenGate is expected to enhance RFIC simulation speed and capacity with negligible loss in accuracy. Jivaro-for-GoldenGate is designed in cooperation with edXact, a company that provides high-precision, high-performance technology for backend physical verification. edXact’s Jivaro-A netlist-reduction engine is the core of this new RFIC design software.