Hybrid ASIC is a standard cell implementation optimized for density and it includes an integrated, pre-defined Structured ASIC core. The ... ... derivative products and fast re-spins. Typical applications include systems that require a variety of video compression schemes, data encryption and pre-standard protocol implementations. Hybrid ASICs combine embedded metal-configurable digital logic with standard cell logic, Input/Output (I/O), memory and mixed ...

The new solution IP Elements help engineers to quickly design with features of the PSoC 3 architecture such as the ... ... and flexibility of the new platform... PSoC 3 Chart(Picture: Cypress)   Press Release: Cypress Provides Solutions IP for New PSoC® 3 Devices and Revolutionary PSoC Creator™ IDE Free Example Projects at www.cypress.com Allow Embedded Developers to Implement Designs More Quickly with Easily-Replicated, Robust IP ...

Cypress has licensed a broad range of intellectual property (IP) from ARM for use in next-generation programmable platforms. Cypress has ... ... blocks, and memory on a single chip. Cypress also offers programmable controllers for touch sensing and touchscreens, programmable clocks, and programmable LED controllers. The combination of the Cortex-M3 processor’s ultra low-power, high-performance credentials with the flexibility of Cypress’s embedded ...

Altera's Serial RapidIO MegaCore function is designed to the RapidIO interconnect specification version 1.3. The core supports x1 and x4 ... ... can create custom systems to support their RapidIO architectures, including processor endpoints, digital signal processor endpoints with signal processing megafunctions, RapidIO switches, and a variety of RapidIO bridges that include PCI, PCI-X, HyperTransport™, system memory, and peripheral devices...   Press Release: Altera's ...

High Speed Syncronous Interface (HSI) is a fullduplex, low latency protocol, that is optimized for die-level interconnect between an Application ... ... platforms. The layered HSI Software Stack is architected to be easily portable to multiple OS’s and hardware platforms. The stack can also be used on SoC’s that have multiple HSI interfaces. The stack supports multiple priority levels per logical ...