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IP Core, Intellectual Property

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Tensilica Announces Stanford University’s Use Tensilica’s Xtensa LX2 Configurable Processor

By pur, at Friday, February 29th, 2008, in IC, Chip, SoC, IP Core, Microcontroller, Microprocessor

  The Stanford team configured Xtensa as 3-way issue VLIW processors with seven stage pipeline, 64 general purpose registers, a 32-bit floating point using the TIE (Tensilica Instruction Extension) Language. Two Tensilica processors are placed in a tile, along with a number of programmable memory mats..

 

Xilinx Announces Free Hardware Reference Design and Avalon IP for SFI-5 Interface

By pur, at Wednesday, March 5th, 2008, in Free, Open Source, IP Core, Programmable Logic, Reference Design

  The reference design accelerates the development of wired networking systems requiring 40Gbps payload rates. The reference design has been hardware verified on the Xilinx ML525 evaluation platform and characterized for skew, temperature, process, and voltage variations to ensure reliable interface, compatible with the OIF SFI-5 standard..

 

Tensilica Announces That WiLinx has licensed the Xtensa LX2 configurable processor

By pur, at Wednesday, March 5th, 2008, in IP Core, Wireless

  Tensilica licensed the Xtensa LX2 configurable processor for its low-power True-UWBTM single chip CMOS (Complementary Metal-Oxide-Semiconductor) solutions. WiLinx has developed key technology that will enable over-the-air, 480 Mbps links across all 12 WiMedia channels in cost-effective CMOS process technology..

 

Synopsys Announces DesignWare coolSRAM-1T Embedded Memory IP in Bulk Logic CMOS

By pur, at Thursday, March 6th, 2008, in IP Core, Memory, Semiconductor

  coolSRAM-1TTM Memory IP Content and feature-rich products require faster, more power-efficient SoCs with increasingly large amounts of on-chip memory. The DesignWare coolSRAM-1T memory IP is a compiler-based solution providing designers with immediate access to the specific memory IP instance they need without any compromise on instance storage capacity or topology..

 

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