Entries summary:

• Smart Memories, Xtensa Lx2 Configurable
• Xilinx, Avalon Ip
• Xtensa Lx2, Xtensa Lx2 Configurable
• Coolsram 1t, Logic Cmos Synopsys

  The Stanford team configured Xtensa as 3-way issue VLIW processors with seven stage pipeline, 64 general purpose registers, a 32-bit floating point using the TIE (Tensilica Instruction Extension) Language. Two Tensilica processors are placed in a tile, along with a number of programmable memory mats..

  The reference design accelerates the development of wired networking systems requiring 40Gbps payload rates. The reference design has been hardware verified on the Xilinx ML525 evaluation platform and characterized for skew, temperature, process, and voltage variations to ensure reliable interface, compatible with the OIF SFI-5 standard..

  Tensilica licensed the Xtensa LX2 configurable processor for its low-power True-UWBTM single chip CMOS (Complementary Metal-Oxide-Semiconductor) solutions. WiLinx has developed key technology that will enable over-the-air, 480 Mbps links across all 12 WiMedia channels in cost-effective CMOS process technology..

  coolSRAM-1TTM Memory IP Content and feature-rich products require faster, more power-efficient SoCs with increasingly large amounts of on-chip memory. The DesignWare coolSRAM-1T memory IP is a compiler-based solution providing designers with immediate access to the specific memory IP instance they need without any compromise on instance storage capacity or topology..