The FM28V100 is new parallel and serial F-RAM products that offer higher-speed read/write performance, lower voltage operation, and optional device features. The FM28V100 is an ideal upgrade from 1Mb battery-backed SRAM in industrial control, metering, medical, automotive, military, gaming, and computing applications, among others. The FM28V100 provides an easy upgrade path for battery-backed or NVSRAM users that want to eliminate batteries or external capacitors from their systems…
Ramtron Announces Faster and Power Flexible 1-Megabit Parallel F-RAM
First parallel device in a family of new high-speed F-RAM devices from Ramtron
SLEC is an essential verification solution for design teams developing leading electronic products. SLEC is the cornerstone of advanced system-level design flows, including those using high-level synthesis (HLS) tools such as Mentor Graphics’ Catapult® C and Forte Design Systems’ Cynthesizer[tm]. The latest release of SLEC supports ac_fixed and cynw_fixed dataypes that are commonly used in wireless designs to model digital signal processing algorithms such as Fast Fourier Transforms and Reed Solomon decoders. SLEC comprehensively verifies the register transfer level (RTL) implementation generated by HLS without running time consuming simulations…
Calypto Announces New SLEC Release for Comprehensive Verification of Wireless, Video, Image Processing System-on-Chip Designs
Latest Capabilities Support Fixed-Point Datatypes, System-Level Memory Interfaces
The DFI specification 2.1 extends support to the latest LPDDR2 memory technology and enables new features including frequency change support and low-power PHY options. The collaborative technical working group includes representatives from ARM, Denali, Intel, LSI, Samsung, and STMicroelectronics. This technical group is enhancing the specification with several low-power features aimed at speeding LPDDR memory system design and integration, and reducing verification costs. The DFI specification 2.1 enables a new low-power PHY interface that enables the controller to provide information to the PHY about the state of the system…
DFI Technical Group Releases Low Power Features with New DDR PHY Interface Specification Version 2.1
DFI Specification Available at the New Community Website Aimed At Growing DFI Ecosystem