Entries summary:

• Advantest, Ddr3 Sdram
• Ddr Phy, Ddr Phy Interface
• Memory, Phy Ip
• Nand Flash, Gbdriver Hs1 Solid

The T5503 was developed specifically to address the challenges of high-volume production test of next-generation high-speed DDR3-SDRAM memory. Next-generation DDR3-SDRAM boasts low power consumption through a reduced operating voltage of 1.5V, compared to the DDR2-SDRAM's 1.8V, as well as higher speed and higher volume data processing..

The Release of DDR PHY Interface (DFI) Specification Version 2.0 extends support to include DDR1, DDR2, Mobile, and DDR3 memory; adds read, write, and gate training interfaces; and improves upon the interoperability features between the memory controller and a DDR PHY.This specification allows designers a standard that has wide industry acceptance and ensures that the controller and PHY will work optimally together and no changes will be required to the hardened logic, resulting in reduced cost, time-to-market, and increasing reusable system IP..

Databahn(TM) DRAM memory controller and hard PHY IP with full DDR3 dual in-line memory module (DIMM) support designed for bulk-memory and caching applications, including networking, storage and personal computing. The DDR3 DIMM is a high-volume product used by SoC customers who require a large amount of high-bandwidth memory..

SSDs that use NAND flash memory are employed in industrial system hardware and laptop PCs. SSDs comprise the flash memory that stores data, a controller that controls the flash memory and makes SSDs appear to be the equivalent of PC hard disc drives, supporting circuits, and mechanical components. The HS1 series of SSDs are the first products to use the GBDriver HS1 SSD controller developed by TDK..