The EasyLCD platform consists of a system baseboard, an FPGA mezzanine module and a TFT LCD display module. The EasyLCD system can be used to develop video and display systems, or it can be integrated into OEM video and display applications. The main component of the EasyLCD system is a reconfigurable FPGA-based video controller that can support LatticeECP2[tm] FPGAs with densities from 12K to 50K LUTs in package sizes up to 484-ball fpBGA. The LatticeECP2 FPGA devices have been optimized to deliver high performance features in an economical FPGA fabric. The devices include Look-Up Table (LUT)-based logic, distributed and embedded memory, Phase Locked Loops (PLLs), Delay Locked Loops (DLLs), pre-engineered source synchronous I/O support, enhanced sysDSP[tm] blocks and advanced configuration support…

CONFIGURABLE VIDEO PLATFORM NOW AVAILABLE FOR THE LatticeECP2 FPGA FAMILY

Arrow Electronics and Exor/Sitek International Develop a Flexible Image Processing Platform that Includes Boards and Intellectual Property for the LatticeECP2 FPGA

ispLEVER Classic v1.2 Design Tool Suite supports all Lattice SPLD, CPLD and select FPGA families. ispLEVER Classic v1.2 Design Tool Suite now provide full production support for the recently released ultra low power ispMACH® 4000ZE CPLD family and also include user-friendly support for several innovative new silicon functions. ispLEVER Classic 1.2 also includes the newest versions of Synopsys’ Synplify synthesis and Aldec’s Active-HDL simulator EDA tools. The release of the ispLEVER Classic tool suite offers users immediate access to Lattice’s exciting new PLD technology…

LATTICE ispLEVER CLASSIC DESIGN TOOLS NOW SUPPORT NEW CPLD FAMILY

Full Production Support for Ultra Low Power ispMACH 4000ZE CPLDs

Lattice Semiconductor Corporation (NASDAQ: LSCC) announced the immediate availability of its ispLEVER® Classic version 1.2 design tool suite. The tool suite supports all Lattice SPLD, CPLD and select FPGA families. Lattice’s ispLEVER Classic tools now provide full production support for the recently released ultra low power ispMACH® 4000ZE CPLD family and also include user-friendly support for several innovative new silicon functions. ispLEVER Classic 1.2 also includes the newest versions of Synopsys’ Synplify synthesis and Aldec’s Active-HDL simulator EDA tools.

The JazzFiber-V5 module provides the fastest available solution for single and multichannel ANSI/VITA 17.1-2003 Serial FPDP interfaces with the hardware, firmware and software features to support the emerging VITA 17.2 standard for Serial FPDP extensions. The JazzFiber-V5 is designed from the ground up to operate effectively in laboratory, rugged air-cooled, and rugged conduction-cooled environments meeting the needs of R&D and deployed applications. The JazzFiber-V5 implements the Serial Front Panel Data Port (FPDP) protocol, an open standard for sensor-to-processor data links defined by ANSI/VITA 17.1-2003…

JAZZFIBER-V5 SERIAL FPDP I/O MODULE BREAKS PERFORMANCE BARRIERS IN BOTH PMC AND XMC ARCHITECTURES

Raises the Performance Bar: First to Use Virtex-5, DDR3, Highest Memory Capacity, Speed and Aggregate Throughput