Toshiba Announces MIPI IP Compliant System-on-Chip (SoC) Designs for Mobile Phones and Associated Devices

By pur, Friday, July 3rd, 2009
Category: Embedded Device, IC, Chip, SoC, Microcontroller, Microprocessor, Mobile Devices

The Toshiba MIPI (Mobile Industry Processor Interface) offering comprises a physical layer and protocols that build on this layer to support the rapid development of complete MIPI-compliant transmit and receive solutions. Toshiba’s MIPI D-PHY is a bi-directional, low-power, high-speed physical layer to which various protocols can be added dependant on application requirements. At present MIPIcompliant protocols from Toshiba include CSI-2 (Camera Serial Interface 2), DSI (Display Serial Interface) and UniProSM (Unified Protocol). Toshiba’s MIPI D-PHY provides a re-usable physical layer with support for one to four data channels and a single clock channel. The same D-PHY can be used to for high-speed serial communications in high speed (HS) mode and with single-ended transmission lines in low power (LP) mode…

MIPI-IP-solution-for-SoC

MIPI IP solution for SoC development
(Picture: Toshiba)


Related posts:

  1. Synopsys Announces Immediate Availability of DesignWare MIPI M-PHY IP for Next-Generation High-Speed Interfaces
  2. Agilent Unveils MIPI D-PHY Protocol Test Solution
  3. Arasan Chip Systems Releases MIPI(R) High Speed Synchronous Interface (HSI) Controller IP and Software Stack
  4. MIPI Alliance Introduces 7 Key Standard Specifications for Optimized and Efficient Mobile Terminals
  5. Toshiba Electronics Europe Announces TMPA913CHAXBG, Low-Power ARM9 Microcontroller for Industrial Designs
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chip soc designs, single ended transmission