TSMC Announces 65-Nanometer (nm) Multi-Time Programmable (MTP) Non-Volatile Memory (NVM) Process Technology
By pur, Friday, July 3rd, 2009
Category: Memory, Programmable Logic, Security
65-nanometer (nm) multi-time programmable (MTP) non-volatile memory (NVM) process technology is the first 2.5 volt MTP process, breaking the heretofore 3.3 volt baseline barrier. It eliminates the need for an external EEPROM currently in many systems applications, thereby reducing power, area and costs while increasing data security. the new MTP technology features up to 8k bits memory size that is ideal for small memory requirements associated with MP3 music downloadable digital rights management, RFID devices, fingerprint identification applications, and pre-paid cash or phone cards. The 65nm MTP process is built up to 10 metal layers using copper low-k interconnects and nickel silicide transistor interconnects. The technology is fully logic-compatible and the NVM memory requires no additional processes or masks…
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